Servers are the workhorses in every data center, tasked with data processing and running cloud-based applications. In order to scale the processing infrastructure to satisfy increased workload demand, hyperscale operators are quickly adopting PCI-Express Gen4 and Gen5, increasing the number of PCI-Express ports to enable workload accelerators and SSDs, and utilizing combinations different processor platform architectures. We offer a large portfolio of highly integrated, low-jitter programmable clock generators and fixed-function PCIe Gen1/2/3/4/5 clock generators and buffers ideally suited for all types of server architectures, regardless of CPU vendor platform.
For many years the trend in server platform development has been to integrate clock generation into a larger chipset in order to achieve cost benefits, however significant increases in data rates and bandwidth and migration to synchronized architectures are reversing that course and separating the clock function, which results in architectural performance benefits that outweigh possible cost savings. Silicon Labs maintains close relationships with all server platform suppliers in the market, are fully knowledgeable on the clock trees specific to each one and offer a wide portfolio of timing products meeting the respective timing requirements. We recommend considering the following when outlining your clock tree and selecting the ideal clock generator:
Platform Requirements: Timing requirements in the server market have typically been outlined in the platform reference design from a small subset of CPU suppliers. As data center workloads change, hyperscale operators are migrating to more customized platform solutions from a wider array of suppliers, sometimes opting to develop them internally. Following the recommended guidelines provided within a platform reference design remains standard practice, however we encourage server designers to look beyond the timing solutions used on reference designs to realize benefits that can be achieved by taking advantage of the features and performance available in our latest generation clock generators to enhance your system design.
PCIe Timing: PCI-Express is the primary data bus used throughout server designs. Regardless of PCIe architecture being used, all PCIe endpoints need a low-jitter, differential reference clock meeting the standards set by the PCI-SIG. Server platforms are largely adopting the Gen4 standard today, with plans for a rapid migration to Gen5 in the near future. We offer portfolios of standalone PCIe Gen1/2/3/4/5 clock generators with industry leading phase jitter performance, providing a significant amount of added guardband to the overall system jitter budget. As a contributing PCI-SIG working group member, Silicon Labs helps define PCIe reference clock requirements, and has been the market leader in delivering next generation PCIe Gen4/5 timing products. Our Si522xx PCIe clocks and Si532xx PCIe buffers feature highly integrated HCSL output drivers that can match 85ohm or 100ohm transmission lines without any external termination, minimizing PCB area and cost. Properly measuring jitter on a PCIe reference clock is not straightforward, so to simplify the process and eliminate confusion, we developed the PCIe Clock Jitter Tool. Download the tool for free and learn about PCIe timing by visiting our PCIe Learning Center.
Performance: Many platforms require a mix of PCIe and other high-speed differential clocks with stringent jitter performance requirements. Our Si5332 any-frequency programmable clock generators are capable of synthesizing up to 12 clock outputs, include both PCIe Gen1/2/3/4/5 clocks as well as other frequencies needed within the system design at performance levels below 300fs RMS. Silicon Labs’ clock generators are classified by RMS phase jitter performance level, making it easy to select the right device matching your specific requirements.
Frequency Flexibility: Server designs commonly need a combination of different frequencies, with different output format levels, at different output voltages. Silicon Labs' patented MultiSynth output divider technology provides 0ppm synthesis error on both integer and fractional related output frequencies on up to 12 outputs, while maintaining industry best jitter performance. Our Si5332 programmable clock generators were designed to meet the needs of modern-day server design.
Feature Set and Integration: Silicon Labs’ clock generators come equipped with many value added features that can simplify your design, such as dual spread spectrum loops for EMI reduction on PCIe clocks, frequency selection capability, configurable output enable control, multi-profile selection, and integrated crystal reference source. We know that jitter performance is of the highest importance, so our clock generators include on-chip LDOs on all power pins, resulting in industry best PSNR performance. Suppressing external power supply and board level noise on-chip greatly reduces the number of external components needed for power filtering, reducing board space and cost, and ensures that output clock jitter performance meetings the datasheet specification limits.
Customization: Our ClockBuilder Pro software tool guides you through an easy, step-by-step process to generate a configuration file specific to your clock tree requirements. When the configuration file is complete, ClockBuilder Pro can assign a customized part number specific to your design, provide an associated datasheet addendum, and allow you to save it for future use.
Availability: Sourcing components on short notice to meet prototype or production builds can be challenging. Our solutions-oriented approach to developing flexible, programmable silicon that can be easily configured using ClockBuilder Pro allows for seamless integration within our manufacturing flow to support pre-programmed samples in less than 2 weeks, and production quantities in as little as 4 weeks. Our field programmer also provides the capability to program blank devices on a moment’s notice, or re-configure a device using I2C.