As connectivity bandwidth and data rates continue to increase, RMS phase jitter on SerDes reference clocks become a critical performance factor within the system design. In this webinar, Greg will provide a detailed overview of the types and elements of clock jitter that affect SerDes performance and reference clock jitter budgets. He will also summarize common reference clock requirements in 56G/112G SerDes applications, and introduce Silicon Labs’ triple play of timing products, which are optimized for 100G/400G/800G platforms that use 56G/112G SerDes devices.
Director of Design Engineering
Greg Richmond has over 30 years of experience designing timing products, working with strategic reference design partners, end customers, and is a member of OIF-CEI, PCI-SIG, and various IEEE standards committees. He has 20 patents issued in the area of integrated timing circuits and holds an MSEE from Stanford University and BSEE from Walla Walla University.
45 Minute Presentation
15 Minute Q&A
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