|
|
ARM Cortex-M4
|
40
|
128
|
32
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
20
|
8.1
|
-126.4 (600 bps GFSK 915 MHz)
|
0
|
0
|
87
|
20
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
16
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN32
|
5x5
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
128
|
32
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
20
|
8.1
|
-126.4 (600 bps GFSK 915 MHz)
|
0
|
0
|
87
|
20
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
31
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN48
|
7x7
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
256
|
32
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
20
|
8.1
|
-126.4 (600 bps GFSK 915 MHz)
|
0
|
0
|
87
|
20
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
16
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN32
|
5x5
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
256
|
32
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
20
|
8.1
|
-126.4 (600 bps GFSK 915 MHz)
|
0
|
0
|
87
|
20
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
32
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN48
|
7x7
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
256
|
32
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
20
|
8.1
|
-126.4 (600 bps GFSK 915 MHz)
|
87
|
20
|
87
|
20
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
16
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
125
|
QFN32
|
5x5
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
256
|
32
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
20
|
8.1
|
-126.4 (600 bps GFSK 915 MHz)
|
0
|
0
|
—
|
—
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
31
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
125
|
QFN48
|
7x7
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
64
|
16
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
20
|
8.1
|
-126.4 (600 bps GFSK 915 MHz)
|
0
|
0
|
87
|
20
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
16
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN32
|
5x5
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
64
|
16
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
20
|
8.1
|
-126.4 (600 bps GFSK 915 MHz)
|
0
|
0
|
87
|
20
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
31
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN48
|
7x7
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
128
|
32
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
19.5
|
8.7
|
-99 (250 kbps DSSS-OQPSK 2.4 GHz)
|
133
|
19.5
|
8.8
|
0
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
16
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN32
|
5x5
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
128
|
32
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
19.5
|
8.7
|
-99 (250 kbps DSSS-OQPSK 2.4 GHz)
|
133
|
19.5
|
8.8
|
0
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
31
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN48
|
7x7
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
256
|
32
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
19.5
|
8.7
|
-99 (250 kbps DSSS-OQPSK 2.4 GHz)
|
133
|
19.5
|
8.8
|
0
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
16
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN32
|
5x5
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
256
|
32
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
19.5
|
8.7
|
-99 (250 kbps DSSS-OQPSK 2.4 GHz)
|
133
|
19.5
|
8.8
|
0
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
31
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN48
|
7x7
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
64
|
16
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
19.5
|
8.7
|
-99 (250 kbps DSSS-OQPSK 2.4 GHz)
|
133
|
19.5
|
8.8
|
0
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
16
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN32
|
5x5
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
64
|
16
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
19.5
|
8.7
|
-99 (250 kbps DSSS-OQPSK 2.4 GHz)
|
133
|
19.5
|
8.8
|
0
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
31
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN48
|
7x7
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
128
|
32
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
20
|
8.1
|
-126.4 (600 bps GFSK 915 MHz); -99 (250 kbps DSSS-OQPSK 2.4 GHz)
|
126.7
|
19.5
|
87
|
20
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
28
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN48
|
7x7
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
256
|
32
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
20
|
8.1
|
-126.4 (600 bps GFSK 915 MHz); -99 (250 kbps DSSS-OQPSK 2.4 GHz)
|
126.7
|
19.5
|
87
|
20
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
31
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN48
|
7x7
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
64
|
16
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
20
|
8.1
|
-126.4 (600 bps GFSK 915 MHz); -99 (250 kbps DSSS-OQPSK 2.4 GHz)
|
126.7
|
19.5
|
87
|
20
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
31
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN48
|
7x7
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
128
|
16
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
16.5
|
8.1
|
-126.4 (600 bps GFSK 915 MHz)
|
0
|
0
|
87
|
20
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
16
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN32
|
5x5
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
128
|
16
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
16.5
|
8.1
|
-126.4 (600 bps GFSK 915 MHz)
|
0
|
0
|
87
|
20
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
31
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN48
|
7x7
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
256
|
32
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
16.5
|
8.1
|
-126.4 (600 bps GFSK 915 MHz)
|
0
|
0
|
87
|
20
|
|
|
AES-128
AES-256
SHA-1
SHA-2
|
16
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN32
|
5x5
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
256
|
32
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
16.5
|
8.1
|
-126.4 (600 bps GFSK 915 MHz)
|
0
|
0
|
87
|
20
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
32
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN48
|
7x7
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
32
|
8
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
16.5
|
8.1
|
-126.4 (600 bps GFSK 915 MHz)
|
0
|
0
|
87
|
20
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
16
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN32
|
5x5
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
32
|
8
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
16.5
|
8.1
|
-126.4 (600 bps GFSK 915 MHz)
|
0
|
0
|
87
|
20
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
32
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN48
|
7x7
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
64
|
16
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
16.5
|
8.1
|
-121 dBm (2.4 kbps 2 GFSK 0.1% BER)
|
0
|
0
|
87
|
20
|
|
|
AES-128
AES-256
SHA-1
SHA-2
|
16
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN32
|
5x5
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
64
|
16
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
16.5
|
8.1
|
-126.4 (600 bps GFSK 915 MHz)
|
0
|
0
|
87
|
20
|
|
|
AES-128
AES-256
SHA-1
SHA-2
|
31
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN48
|
7x7
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
128
|
16
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
16.5
|
8.7
|
-99 (250 kbps DSSS-OQPSK 2.4 GHz)
|
88
|
16.5
|
34.1
|
10.5
|
|
|
AES-128
AES-256
SHA-1
SHA-2
|
16
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN32
|
5x5
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
128
|
16
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
16.5
|
8.7
|
-99 (250 kbps DSSS-OQPSK 2.4 GHz)
|
88
|
16.5
|
34.1
|
10.5
|
|
|
AES-128
AES-256
SHA-1
SHA-2
|
31
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN48
|
7x7
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
256
|
32
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
16.5
|
8.7
|
-99 (250 kbps DSSS-OQPSK 2.4 GHz)
|
88
|
16.5
|
34.1
|
10.5
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
16
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN32
|
5x5
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
256
|
32
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
16.5
|
8.7
|
-99 (250 kbps DSSS-OQPSK 2.4 GHz)
|
88
|
16.5
|
34.1
|
10.5
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
31
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN48
|
7x7
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
32
|
8
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
16.5
|
8.7
|
-99 (250 kbps DSSS-OQPSK 2.4 GHz)
|
88
|
16.5
|
34.1
|
10.5
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
16
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN32
|
5x5
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
32
|
8
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
16.5
|
8.7
|
-99 (250 kbps DSSS-OQPSK 2.4 GHz)
|
88
|
16.5
|
34.1
|
10.5
|
|
|
AES-128
AES-256
ECC
SHA-1
SHA-2
|
31
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN48
|
7x7
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
64
|
16
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
16.5
|
8.7
|
-99 (250 kbps DSSS-OQPSK 2.4 GHz)
|
88
|
16.5
|
34.1
|
10.5
|
|
|
AES-128
AES-256
SHA-1
SHA-2
|
16
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN32
|
5x5
|
JTAG, SW
|
|
|
ARM Cortex-M4
|
40
|
64
|
16
|
1 x I²C
1 x I²S
2 x SPI
3 x UART
2 x USART
|
-30
16.5
|
8.7
|
-99 (250 kbps DSSS-OQPSK 2.4 GHz)
|
88
|
16.5
|
34.1
|
10.5
|
|
|
AES-128
AES-256
SHA-1
SHA-2
|
31
|
12-bit, SAR, 1 Msps
|
iDAC
|
|
|
7
|
|
2
|
-40
85
|
QFN48
|
7x7
|
JTAG, SW
|